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ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ
Data Sheet September 29, 2008 FN6792.0
High Performance Industry Standard Single-Ended Current Mode PWM Controller
The ISL884xAMBEPZ is a high performance drop-in replacement for the popular 28C4x and 18C4x PWM controllers suitable for a wide range of power conversion applications including boost, flyback, and isolated output configurations. Its fast signal propagation and output switching characteristics make this an ideal product for existing and new designs. Features include 30V operation, low operating current, 90A start-up current, adjustable operating frequency to 2MHz, and high peak current drive capability with 20ns rise and fall times.
PART NUMBER ISL8840AMBEPZ ISL8841AMBEPZ ISL8842AMBEPZ ISL8843AMBEPZ ISL8844AMBEPZ ISL8845AMBEPZ RISING UVLO (V) 7.0 7.0 14.4 8.4 14.4 8.4 MAX. DUTY CYCLE (%) 100 50 100 100 50 50
Features
* Full Mil-Temp Electrical Performance from -55C to +125C * Controlled Baseline with One Wafer Fabrication Site and One Assembly/Test Site * Full Homogenous Lot Processing in Wafer Fab * No Combination of Wafer Fabrication Lots in Assembly * Full Traceability Through Assembly and Test by Date/Trace Code Assignment * Enhanced Process Change Notification * Enhanced Obsolescence Management * Eliminates Need for Up-Screening a COTS Component * 1A MOSFET Gate Driver * 90A Start-up Current, 125A Maximum * 35ns Propagation Delay Current Sense to Output * Fast Transient Response with Peak Current Mode Control * 30V Operation * Adjustable Switching Frequency to 2MHz * 20ns Rise and Fall Times with 1nF Output Load * Trimmed Timing Capacitor Discharge Current for Accurate Deadtime/Maximum Duty Cycle Control * 1.5MHz Bandwidth Error Amplifier
Pinout
ISL884XAMBEPZ (8 LD SOIC) TOP VIEW
COMP 1 FB 2 CS 3 RTCT 4 8 VREF 7 VDD 6 OUT 5 GND
* Tight Tolerance Voltage Reference Over Line, Load and Temperature * 3% Current Limit Threshold * Pb-Free (RoHS Compliant)
Applications
* Isolated Flyback and Forward Regulators * Boost Regulators
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ
Ordering Information
PART NUMBER (Notes 1, 2) ISL8840AMBEPZ ISL8841AMBEPZ ISL8842AMBEPZ ISL8843AMBEPZ ISL8844AMBEPZ ISL8845AMBEPZ NOTES: 1. Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. PART MARKING 8840A MBEPZ 8841A MBEPZ 8842A MBEPZ 8843A MBEPZ 8844A MBEPZ 8845A MBEPZ TEMP RANGE (C) -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC PKG. DWG. # M8.15 M8.15 M8.15 M8.15 M8.15 M8.15
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FN6792.0 September 29, 2008
Functional Block Diagram
ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ
VDD START/STOP UV COMPARATOR + + GND 2.5V A A = 0.5 VDD OK ENABLE
VREF 5.00V
VREF
VREF FAULT
+
VREF UV COMPARATOR 4.65V 4.80V + -
3
CS FB COMP VREF 100k 2.9V 1.0V 150k RTCT
FN6792.0 September 29, 2008
PWM COMPARATOR 100mV + + 2R + ERROR AMPLIFIER VF TOTAL = 1.15V R T Q OUT SQ 36k RQ RESET DOMINANT
1.1V CLAMP
ONLY ISL8841AMBEPZ/ ISL8844AMBEPZ/ ISL8845AMBEPZ Q
ON OSCILLATOR COMPARATOR <10ns + 8.4mA ON CLOCK
ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . GND -0.3V to +30V OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VDD + 0.3V Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
Thermal Information
Thermal Resistance (Note 4) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Supply Voltage Range (Note 3) . . . . . . . . . . . . . . . . . . . . . 9V to 30V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-55C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 3. All voltages are with respect to GND. 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Technical Brief TB379 for details.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 3. VDD = 15V, Rt = 10k, Ct = 3.3nF, TA = -55 to +125C, Typical values are at TA = +25C. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER UNDERVOLTAGE LOCKOUT START Threshold (ISL8840AMBEPZ, ISL8841AMBEPZ) START Threshold (ISL8843AMBEPZ, ISL8845AMBEPZ) START Threshold (ISL8842AMBEPZ, ISL8844AMBEPZ) STOP Threshold (ISL8840AMBEPZ, ISL8841AMBEPZ) STOP Threshold (ISL8843AMBEPZ, ISL8845AMBEPZ) STOP Threshold (ISL8842AMBEPZ, ISL8844AMBEPZ) Hysteresis (ISL8840AMBEPZ, ISL8841AMBEPZ) Hysteresis (ISL8843AMBEPZ, ISL8845AMBEPZ) Hysteresis (ISL8842AMBEPZ, ISL8844AMBEPZ) Start-up Current, IDD Operating Current, IDD Operating Supply Current, ID REFERENCE VOLTAGE Overall Accuracy Long Term Stability Current Limit, Sourcing Current Limit, Sinking CURRENT SENSE Input Bias Current CS Offset Voltage COMP to PWM Comparator Offset Voltage Input Signal, Maximum
6.5 8.0 (Note 7) 13.3 6.1 7.3 8.0 VDD < START Threshold (Note 5) Includes 1nF GATE loading -
7.0 8.4 14.3 6.6 7.6 8.8 0.4 0.8 5.4 90 2.9 4.75
7.5 9.0 15.3 6.9 8.0 9.6 125 4.0 5.5
V V V V V V V V V A mA mA
Over line (VDD = 12V to 30V), load, temperature TA = +125C, 1000 hours (Note 6)
4.900 -20 5
5.000 5 -
5.050 -
V mV mA mA
VCS = 1V VCS = 0V (Note 6) VCS = 0V (Note 6)
-1.0 95 0.80 0.97
100 1.15 1.00
1.0 105 1.30 1.03
A mV V V
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FN6792.0 September 29, 2008
ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 3. VDD = 15V, Rt = 10k, Ct = 3.3nF, TA = -55 to +125C, Typical values are at TA = +25C. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested (Continued) TEST CONDITIONS 0 < VCS < 910mV, VFB = 0V MIN 2.5 TYP 3.0 35 MAX 3.5 60 UNITS V/V ns
PARAMETER Gain, ACS = VCOMP/VCS CS to OUT Delay ERROR AMPLIFIER Open Loop Voltage Gain Unity Gain Bandwidth Reference Voltage FB Input Bias Current COMP Sink Current COMP Source Current COMP VOH COMP VOL PSRR OSCILLATOR Frequency Accuracy Frequency Variation with VDD Temperature Stability Amplitude, Peak-to-Peak RTCT Discharge Voltage (Valley Voltage) Discharge Current OUTPUT Gate VOH Gate VOL Peak Output Current Rise Time Fall Time GATE VOL UVLO Clamp Voltage PWM Maximum Duty Cycle (ISL8840AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ) Maximum Duty Cycle (ISL8841AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ) Minimum Duty Cycle NOTES:
(Note 6) (Note 6) VFB = VCOMP VFB = 0V VCOMP = 1.5V, VFB = 2.7V VCOMP = 1.5V, VFB = 2.3V VFB = 2.3V VFB = 2.7V Frequency = 120Hz, VDD = 12V to 30V (Note 6)
60 1.0 2.460 -1.0 1.0 -0.4 4.80 0.4 60
90 1.5 2.500 -0.2 80
2.535 1.0 VREF 1.0 -
dB MHz V A mA mA V V dB
Initial, TA = +25C TA = +25C, (f30V - f10V)/f30V (Note 6) Static Test Static Test RTCT = 2.0V
48 6.2
51 0.2 1.75 1.0 8.0
53 1.0 5 8.5
kHz % % V V mA
VDD - OUT, IOUT = -200mA OUT - GND, IOUT = 200mA COUT = 1nF (Note 6) COUT = 1nF (Note 6) COUT = 1nF (Note 6) VDD = 5V, ILOAD = 1mA COMP = VREF
-
1.0 1.0 1.0 20 20 -
2.0 2.0 40 40 1.2
V V A ns ns V
94.0
96.0
-
%
COMP = VREF
47.0
48.0
-
%
COMP = GND
-
-
0
%
5. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current. 6. Limits established by characterization and are not production tested. 7. Adjust VDD above the start threshold and then lower to 15V.
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FN6792.0 September 29, 2008
ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ
Typical Performance Curves
1.01 NORMALIZED FREQUENCY 1.001 NORMALIZED VREF 0 20 40 60 80 100 120 140 1.000 0.999 0.998 0.997 0.996 0.98 -60 -40 -20 0.995 -60 -40 -20 0 20 40 60 80 100 120 140
1.00
0.99
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 1. FREQUENCY vs TEMPERATURE
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
NORMALIZED EA REFERENCE
1.001
103
1.000
FREQUENCY (Hz)
100
100pF 220pF 330pF 470pF
0.998
10
1.0nF 2.2nF 3.3nF 4.7nF 6.8nF
0.997
0.996 -60 -40 -20
1 0 20 40 60 80 TEMPERATURE (C) 100 120 140
1
10 Rt (k)
100
FIGURE 3. EA REFERENCE vs TEMPERATURE
FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN
Pin Descriptions
RTCT - This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by connecting a resistor, Rt, between VREF and this pin and a timing capacitor, Ct, from this pin to GND. The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The charge time, tC, the discharge time, tD, the switching frequency, f, and the maximum duty cycle, DMAX, can be approximated from the following equations:
t C 0.533 R t C t 0.008 R t - 3.83 t D - R t C t In ------------------------------------------ 0.008 R t - 1.71 (EQ. 1)
COMP - COMP is the output of the error amplifier and the input of the PWM comparator. The control loop frequency compensation network is connected between the COMP and FB pins. FB - The output voltage feedback is connected to the inverting input of the error amplifier through this pin. The non-inverting input of the error amplifier is internally tied to a reference voltage. CS - This is the current sense input to the PWM comparator. The range of the input signal is nominally 0V to 1.0V and has an internal offset of 100mV. GND - GND is the power and small signal reference ground for all functions. OUT - This is the drive output to the power switching device. It is a high current output capable of driving the gate of a power MOSFET with peak currents of 1.0A. This GATE output is actively held low when VDD is below the UVLO threshold. VDD - VDD is the power connection for the device. The total supply current will depend on the load applied to OUT. Total IDD current is the sum of the operating current and the average output current. Knowing the operating frequency, f,
(EQ. 2)
f = 1 (tC + tD)
D = tC f
(EQ. 3) (EQ. 4)
The formulae have increased error at higher frequencies due to propagation delays. Figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency.
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FN6792.0 September 29, 2008
ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ
and the MOSFET gate charge, Qg, the average output current can be calculated from Equation 5:
I OUT = Qg x f (EQ. 5)
affects COMP. During power-down, diode D1 quickly discharges C1 so that the soft-start circuit is properly initialized prior to the next power-on sequence.
Gate Drive
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. VREF - The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. Bypass to GND with a 0.1F to 3.3F capacitor to filter this output as needed. The ISL884xAMBEPZ is capable of sourcing and sinking 1A peak current. To limit the peak current through the IC, an optional external resistor may be placed between the totem-pole output of the IC (OUT pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance.
Functional Description
Features
The ISL884xAMBEPZ current mode PWM makes an ideal choice for low-cost flyback and forward topology applications. With its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating.
Slope Compensation
For applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. For applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. Slope compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the voltage feedback error signal. Adding the external ramp to the current feedback signal is the more popular method. From the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, Fm, without slope compensation, is in Equation 6.
1 Fm = ----------------S n t SW
VREF ISL884xAMBEPZ
Oscillator
The ISL884xAMBEPZ has a sawtooth oscillator with a programmable frequency range to 2MHz, which can be programmed with a resistor from VREF and a capacitor to GND on the RTCT pin. (Please refer to Figure 4 for the resistor and capacitance required for a given frequency.)
Soft-Start Operation
Soft-start must be implemented externally. One method, illustrated in Figure 5, clamps the voltage on COMP.
(EQ. 6)
D1
R1 Q1
COMP
where Sn is the slope of the sawtooth signal and tsw is the duration of the half-cycle. When an external ramp is added, the modulator gain becomes Equation 7:
1 1 Fm = ----------------------------------- = -------------------------( S n + S e )t SW m c Snt SW (EQ. 7)
C1
GND
where Se is slope of the external ramp and
Se m c = 1 + -----Sn (EQ. 8)
FIGURE 5. SOFT-START
The COMP pin is clamped to the voltage on capacitor C1 plus a base-emitter junction by transistor Q1. C1 is charged from VREF through resistor R1 and the base current of Q1. At power-up C1 is fully discharged, COMP is at ~0.7V, and the duty cycle is zero. As C1 charges, the voltage on COMP increases, and the duty cycle increases in proportion to the voltage on C1. When COMP reaches the steady state operating point, the control loop takes over and soft-start is complete. C1 continues to charge up to VREF and no longer
The criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at the switching frequency. The double-pole will be critically damped if the Q-factor is set to 1, over-damped for Q < 1, and under-damped for Q > 1. An under-damped condition may result in current loop instability.
1 Q = ------------------------------------------------ ( m c ( 1 - D ) - 0.5 ) (EQ. 9)
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FN6792.0 September 29, 2008
ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ
where D is the percent of on-time during a switching cycle. Setting Q = 1 and solving for Se yields Equation 10:
1 1 S e = S n -- + 0.5 ------------ - 1 1 -D (EQ. 10)
RtCt signal. A typical application sums the buffered RtCt signal with the current sense feedback and applies the result to the CS pin, as shown in Figure 6.
Since Sn and Se are the on time slopes of the current ramp and the external ramp, respectively, they can be multiplied by tON to obtain the voltage change that occurs during tON.
1 1 V e = V n -- + 0.5 ------------ - 1 1 -D
R9 ISL8843
VREF
(EQ. 11)
R6
CS
where Vn is the change in the current feedback signal (I) during the on-time and Ve is the voltage that must be added by the external ramp. For a flyback converter, Vn can be solved for in terms of input voltage, current transducer components, and primary inductance, yielding
D t SW V IN R CS 1 1 -V e = ------------------------------------------------- -- + 0.5 ------------ - 1 1 -D Lp V (EQ. 12)
RTCT C4
FIGURE 6. SLOPE COMPENSATION
where RCS is the current sense resistor, fSW is the switching frequency, Lp is the primary inductance, VIN is the minimum input voltage, and D is the maximum duty cycle. The current sense signal at the end of the on-time for CCM operation is:
( 1 - D ) VO f N S R CS SW V CS = ------------------------ I O + --------------------------------------------- 2L s NP V (EQ. 13)
Assuming the designer has selected values for the RC filter (R6 and C4) placed on the CS pin, the value of R9 required to add the appropriate external ramp can be found by superposition.
2.05D R 6 V e = --------------------------R6 + R9 V (EQ. 16)
The factor of 2.05 in Equation 16 arises from the peak amplitude of the sawtooth waveform on RtCt minus a base-emitter junction drop. That voltage multiplied by the maximum duty cycle is the voltage source for the slope compensation. Rearranging to solve for R9 yields:
( 2.05D - V e ) R 6 R 9 = --------------------------------------------Ve (EQ. 17)
where VCS is the voltage across the current sense resistor, Ls is the secondary winding inductance, and IO is the output current at current limit. Equation 13 assumes the voltage drop across the output rectifier is negligible. Since the peak current limit threshold is 1.00V, the total current feedback signal plus the external ramp voltage must sum to this value when the output load is at the current limit threshold.
V e + V CS = 1 (EQ. 14)
The value of RCS determined in Equation 15 must be rescaled so that the current sense signal presented at the CS pin is that predicted by Equation 13. The divider created by R6 and R9 makes this necessary.
R6 + R9 R CS = -------------------- R CS R9 (EQ. 18)
Example: VIN = 12V VO = 48V Ls = 800H Ns/Np = 10 Lp = 8.0H IO = 200mA Switching Frequency, fSW = 200kHz Duty Cycle, D = 28.6%
Substituting Equations 12 and 13 into Equation 14 and solving for RCS yields Equation 15:
1 R CS = ---------------------------------------------------------------------------------------------------------------------------------------------------1 -- + 0.5 N ( 1 - D ) V O f sw D f sw V IN s ------------------------------- ----------------- - 1 + ------ I O + ------------------------------------------- 1-D N Lp 2L s p (EQ. 15)
Adding slope compensation is accomplished in the ISL884xAMBEPZ using an external buffer transistor and the
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FN6792.0 September 29, 2008
ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ
R6 = 499 Solve for the current sense resistor, RCS, using Equation 15. RCS = 295m Determine the amount of voltage, Ve, that must be added to the current feedback signal using Equation 12. Ve = 92.4mV Using Equation 17, solve for the summing resistor, R9, from CT to CS. R9 = 2.67k Determine the new value of RCS (R'CS) using Equation 18. R'CS = 350m Additional slope compensation may be considered for design margin. The previous discussion determines the minimum external ramp that is required. The buffer transistor used to create the external ramp from RtCt should have a sufficiently high gain (>200) so as to minimize the required base current. Whatever base current is required reduces the charging current into RtCt and will reduce the oscillator frequency.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a Fault is detected, OUT is disabled. When VREF exceeds 4.80V, the Fault condition clears, and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. VDD should be bypassed directly to GND with good high frequency capacitors.
References
[1] Ridley, R., "A New Continuous-Time Model for Current Mode Control", IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991.
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FN6792.0 September 29, 2008
ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ
Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6792.0 September 29, 2008

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